Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
Electronics Weekly

DSP versus FPGA

In considering the design option for DSP vs. FPGA it is helpful to compare both architectures in a FIR filter application, writes Reg Zatrepalek One of the most widely used digital signal-processing ...
Design-Reuse

Flex Logix Extends Embedded FPGA-in-SoC Architecture with New Block RAM and DSP Cores

Santa Clara, CA -- September 17, 2015 -- Flex Logix, innovative developer of FPGA-in-SoC technology, today announced the extension of its core FPGA logic architecture to include Block RAM (BRAM) and ...
Electronic Design

Understanding FPGA Processor Interconnects

This file type includes high resolution graphics and schematics when applicable. FPGAs are wonderful tools. They consist of a collection of logic cells called lookup tables (LUTs) surrounded by an ...